1. Field
The present invention relates to an auxiliary processing element (PE) for multiplexing (hereinafter, “multiplexing auxiliary PE”) and a semiconductor integrated circuit.
2. Description of the Related Art
Recently, attention has been given to a dynamic reconfigurable circuit and a dynamic reconfigurable semiconductor integrated circuit which are capable of easily achieving ASIC-level performance using parallel operation with a program design similar to that for a digital signal processor (DSP).
The dynamic reconfigurable circuit includes an element (processing element) that performs operation, data storage and flow control, and program flow control, a configuration memory, and a sequencer.
The configuration memory stores a configuration indicating an operation of the PE. The sequencer controls the dynamic reconfigurable circuit.
One of features of the dynamic reconfigurable circuit is that the PE may be effectively reused by switching between configurations at high speed.
Japanese Laid-open Patent Publications Nos. 2006-018539 and 2007-241830 disclose related-art dynamic reconfigurable circuits in which PEs are effectively reused by switching between configurations at high speed.
As for methods of switching between configurations at high speed to effectively reuse PEs, a dynamically reconfigurable processor (DRP) method and a segmentation context switching method have been studied and developed.
In the DRP method, the number of PEs which may be used in one configuration is up to the physical number of PEs. In the segmentation context switching method, one virtual configuration is used, thus increasing the number of virtually available PEs.